Design Engineer Hardware

Eworld Solutions
September 10, 2020
Atlanta, GA
Job Type


RTL Design Engineer (High-Speed IO Controller)

Job Location: Santa Clara, CA / Austin, CA (After COVID) (Currently Remote)

Job Type: Fulltime/Contract

Experience: 10+ Years

Education: BA/BS/MS or Equivalent


Required Skills and Experience

  • Strong fundamentals in digital ASIC design; experience using Verilog or VHDL

  • Experience with ASIC design/micro-architecture, synthesis, timing/power analysis

  • Experience in micro-architecture and/or design of the controller for at least one of the high-speed SerDes interfaces like PCIe, Ethernet, Die2Die, etc.

  • Practical experience with the implementation of the transaction layer, data link layer, and/or the logical physical layer including PCS

  • Expertise in implementation of ordering, buffering and flow control logic

  • Strong understanding of link management and training requirements including power state management

  • Expertise in implementation of RAS features like FEC, CRC and replay features

  • Experience implementing controllers for a multi-protocol PHY is a plus

  • Strong understanding of PIPE interface requirements is highly desired

  • Strong understanding of IO performance issues from the protocol level to the application level

  • Familiarity with high performance and low power design techniques

  • Some experience in design verification and/or physical design is a plus


Roles and Responsibilities

  • Work with Fabric designers and SerDes PHY designers to define optimal interfaces

  • Develop the micro-architecture and write design specifications for a high-speed IO controller factoring in the SoC architecture requirements

  • Work with chip architects to conceive of the micro-architecture and deliver RTL design for the IO controllers interfacing with high-speed SerDes PHYs

  • Convert design spec to Verilog RTL

  • Help with architecture/product definition of the SOC through early involvement in the product life-cycle.

  • Support the verification team to devise appropriate test plans and verification strategy

  • Collaborate with the physical design team to close timing, area targets, reliability, etc

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